assign arbiter_out=arbiter_out_r; assign pc_sel=pc_sel_r; //经过判断后的输出 always @(arbiter_order or arbiter_sel )begin if (arbiter_sel==1'b0) begin arbiter_out_r<=8'b zzzzzzzz; pc_sel_r<=1'b0; end elseif (arbiter_sel==1'b1) begin case(arbiter_order) never: begin arbiter_out_r<=8'b zzzzzzzz; pc_sel_r<=1'b0; end value_zeros: begin if (reg_3==anchoring_number) begin arbiter_out_r<=reg_0; pc_sel_r<=1'b1; end elsebegin arbiter_out_r<=8'b zzzzzzzz; pc_sel_r<=1'b0; end end value_small_zero: begin if (reg_3<anchoring_number) begin arbiter_out_r<=reg_0; pc_sel_r<=1'b1; end elsebegin arbiter_out_r<=8'b zzzzzzzz; pc_sel_r<=1'b0; end end value_small_or_zero: begin if (reg_3<=anchoring_number) begin arbiter_out_r<=reg_0; pc_sel_r<=1'b1; end elsebegin arbiter_out_r<=8'b zzzzzzzz; pc_sel_r<=1'b0; end end Always: begin arbiter_out_r<=reg_0; pc_sel_r<=1'b1; end value_not_equal_zero: begin if (reg_3!=anchoring_number) begin arbiter_out_r<=reg_0; pc_sel_r<=1'b1; end elsebegin arbiter_out_r<=8'b zzzzzzzz; pc_sel_r<=1'b0; end end value_big_or_zero: begin if (reg_3>=anchoring_number) begin arbiter_out_r<=reg_0; pc_sel_r<=1'b1; end elsebegin arbiter_out_r<=8'b zzzzzzzz; pc_sel_r<=1'b0; end end value_big_zero: begin if (reg_3>anchoring_number) begin arbiter_out_r<=reg_0; pc_sel_r<=1'b1; end elsebegin arbiter_out_r<=8'b zzzzzzzz; pc_sel_r<=1'b0; end end endcase end end endmodule